TH-C01 - Revision history

Daniel: /* Architecture Details */

2013-09-05T08:42:04Z

‎Architecture Details

Daniel at 08:40, 5 September 2013

2013-09-05T08:40:28Z

Daniel: Created page with "The TH-C01 is my first designed and built CPU, just using logic elements. The design has been simulated using the logisim tool. ==Definition== * 8 bit ALU * 8 bit Data bus * ..."

2013-05-08T14:59:21Z

Created page with "The TH-C01 is my first designed and built CPU, just using logic elements. The design has been simulated using the logisim tool. ==Definition== * 8 bit ALU * 8 bit Data bus * ..."

New page

The TH-C01 is my first designed and built CPU, just using logic elements. The design has been simulated using the logisim tool.

==Definition==
* 8 bit ALU
* 8 bit Data bus
* 16 bit Address bus (MAX 64k bytes RAM)
* 8 x 8 bit registers (R0..R7) + (R6+R7 as address pointer)
* Dedicated Stack Pointer
* Dedicated PC
* Interruption control
* Expected 100 Khz
* RISC-like architecture with 3 to 5 cycles per operation

==Architecture Details==

===ALU===
The ALU can operate two 8 bit data (A and B), and its composed of 8 elements that are basically the same.
[[File:TH-C01-1b-ALU-Element.png|center|One bit ALU element]]

'''INPUTS'''':
* A: Operand A bit
* B: Operand B bit
* Aon: Enables A bit operand
* Bon: Enables B bit operand
* Ainv: Inverses the A bit operand
* Binv: Inverses the B bit operand
* Cin: Carry in
* Op (2 bits): Chose operation path
* Sinv: Invert the operation result

'''OUTPUTS'''':
*S: Operation result
*Aout:
*Bout:
*Cout: Carry out

@@ Line 30: / Line 30: @@
 '''OUTPUTS'''':
-*S: Operation result
+* S: Operation result
-*Aout:
+* Aout:
-*Bout:
+* Bout:
-*Cout: Carry out
+* Cout: Carry out
 == Instruction Set ==

← Older revision		Revision as of 08:40, 5 September 2013
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	*Bout:		*Bout:
	*Cout: Carry out		*Cout: Carry out
		+
		+	== Instruction Set ==