Difference between revisions of "TSC Register"
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The Time Stamp Counter (TSC) is a 64-bit register present in most modern x86 processors. | The Time Stamp Counter (TSC) is a 64-bit register present in most modern x86 processors. | ||
| + | |||
| + | It counts the number of cycles since reset. | ||
| + | |||
| + | The instruction RDTSC returns the TSC in EDX:EAX | ||
| + | |||
| + | supported out-of-order execution | ||
| + | |||
| + | not necessarily performed in the order they appear in the executable | ||
| + | |||
| + | This can cause RDTSC to be executed later or earlier -> misleading cycle count. | ||
| + | |||
| + | using the RDTSCP instruction, which is a serializing variant of the RDTSC instruction. -> force every preceding instruction to complete | ||
| + | |||
| + | the time-stamp counter increments at a constant rate. That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may differ from the maximum qualified frequency of the processor. | ||
| + | |||
| + | Since the family 10h (Barcelona/Phenom), AMD chips feature a constant TSC. | ||
| + | |||
| + | ---- | ||
| + | |||
| + | From Nehalem | ||
| + | |||
| + | By default the TSC is synchronized across all cores. However, the TSC value of a core could be changed by some software subsystem using the WRMSR instruction. Take a look at quotes below and I hope they finally answer your question: | ||
| + | |||
| + | Intel(R) 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B & 3C): | ||
| + | System Programming Guide | ||
| + | |||
| + | ---- | ||
| + | |||
| + | Need to use "volatile" variables so that the compiler does not change the order. | ||
| + | |||
| + | <pre> | ||
| + | Tsc_t readTsc(void) | ||
| + | { | ||
| + | unsigned hi, lo; | ||
| + | __asm__ __volatile__ ("rdtsc" : "=a"(lo), "=d"(hi)); | ||
| + | return ( (unsigned long long)lo)|( ((unsigned long long)hi)<<32 ); | ||
| + | } | ||
| + | <\pre> | ||
Revision as of 09:20, 6 November 2014
The Time Stamp Counter (TSC) is a 64-bit register present in most modern x86 processors.
It counts the number of cycles since reset.
The instruction RDTSC returns the TSC in EDX:EAX
supported out-of-order execution
not necessarily performed in the order they appear in the executable
This can cause RDTSC to be executed later or earlier -> misleading cycle count.
using the RDTSCP instruction, which is a serializing variant of the RDTSC instruction. -> force every preceding instruction to complete
the time-stamp counter increments at a constant rate. That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may differ from the maximum qualified frequency of the processor.
Since the family 10h (Barcelona/Phenom), AMD chips feature a constant TSC.
From Nehalem
By default the TSC is synchronized across all cores. However, the TSC value of a core could be changed by some software subsystem using the WRMSR instruction. Take a look at quotes below and I hope they finally answer your question:
Intel(R) 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B & 3C): System Programming Guide
Need to use "volatile" variables so that the compiler does not change the order.
Tsc_t readTsc(void)
{
unsigned hi, lo;
__asm__ __volatile__ ("rdtsc" : "=a"(lo), "=d"(hi));
return ( (unsigned long long)lo)|( ((unsigned long long)hi)<<32 );
}
<\pre>
