TSC Register - Revision history

Daniel at 12:40, 12 January 2015

2015-01-12T12:40:14Z

Daniel: /* Notes */

2014-11-09T22:54:35Z

‎Notes

Daniel at 22:53, 9 November 2014

2014-11-09T22:53:36Z

Daniel at 22:49, 9 November 2014

2014-11-09T22:49:01Z

Daniel at 15:06, 7 November 2014

2014-11-07T15:06:06Z

Daniel at 14:43, 7 November 2014

2014-11-07T14:43:26Z

Daniel at 11:23, 6 November 2014

2014-11-06T11:23:13Z

Daniel at 11:22, 6 November 2014

2014-11-06T11:22:41Z

Daniel at 09:20, 6 November 2014

2014-11-06T09:20:39Z

Daniel: Created page with "The Time Stamp Counter (TSC) is a 64-bit register present in most modern x86 processors."

2014-11-06T08:53:45Z

Created page with "The Time Stamp Counter (TSC) is a 64-bit register present in most modern x86 processors."

New page

The Time Stamp Counter (TSC) is a 64-bit register present in most modern x86 processors.

@@ Line 11: / Line 11: @@
 As the compiler might also optimize and reorder code it is necessary to use "volatile" variables.
 <syntaxhighlight lang="c">
 typedef unsigned long long Tsc_t;
@@ Line 23: / Line 24: @@
+Measuring ticks between two TSC reads:
 <syntaxhighlight lang="c">
 #include <stdio.h>
@@ Line 51: / Line 52: @@
+Measuring ticks in one second:
 <syntaxhighlight lang="c">
 #include <stdio.h>

← Older revision		Revision as of 22:54, 9 November 2014
Line 80:		Line 80:

	== Notes ==		== Notes ==
−	~~{{Reflist}}~~	+	<references />

@@ Line 2: / Line 2: @@
 As many modern x86 CPUs support out-of-order execution, the RDTSC will not necessarily be performed in the order that appears in the executable. This can cause the RDTSC instruction to be executed later or earlier than desired misleading cycle count. A serializing variant of the RDTSC instruction is often present, RDTSCP, forcing every preceding instruction to be completed.
 The time-stamp counter increments at a constant rate, that may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by the maximum resolved frequency at which the processor is booted (in older CPUs it was not incrementing constantly, varying with the core's actual frequency). The maximum resolved frequency may differ from the maximum qualified frequency of the processor.
-Since the family 10h (Barcelona/Phenom) for AMD and Nehalem CPUs for Intel, the TSC increases at a constant rate and is synchronized across all cores of the CPU. However, the TSC value of a core could be changed by some software subsystem using the WRMSR instruction.
+Since the family 10h (Barcelona/Phenom) for AMD and Nehalem CPUs for Intel, the TSC increases at a constant rate and is synchronized across all cores of the CPU. However, the TSC value of a core could be changed by some software subsystem using the WRMSR instruction.<ref>Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B & 3C): System Programming Guide</ref>
-(Intel(R) 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B & 3C): System Programming Guide)
+----
 As the compiler might also optimize and reorder code it is necessary to use "volatile" variables.
@@ Line 79: / Line 78: @@
+}
 </syntaxhighlight>

@@ Line 1: / Line 1: @@
-The Time Stamp Counter (TSC) is a 64-bit register present in most modern x86 processors.
+The Time Stamp Counter (TSC) is a 64-bit register present in most modern x86 processors that counts the number of cycles since reset. The instruction RDTSC returns the TSC value in EDX:EAX registers.
-It counts the number of cycles since reset.
+As many modern x86 CPUs support out-of-order execution, the RDTSC will not necessarily be performed in the order that appears in the executable. This can cause the RDTSC instruction to be executed later or earlier than desired misleading cycle count. A serializing variant of the RDTSC instruction is often present, RDTSCP, forcing every preceding instruction to be completed.
-supported out-of-order execution
+The time-stamp counter increments at a constant rate, that may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by the maximum resolved frequency at which the processor is booted (in older CPUs it was not incrementing constantly, varying with the core's actual frequency). The maximum resolved frequency may differ from the maximum qualified frequency of the processor.
-not necessarily performed in the order they appear in the executable
+Since the family 10h (Barcelona/Phenom) for AMD and Nehalem CPUs for Intel, the TSC increases at a constant rate and is synchronized across all cores of the CPU. However, the TSC value of a core could be changed by some software subsystem using the WRMSR instruction.
-This can cause RDTSC to be executed later or earlier -> misleading cycle count.
+(Intel(R) 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B & 3C): System Programming Guide)
 <syntaxhighlight lang="c">

@@ Line 30: / Line 30: @@
 Need to use "volatile" variables so that the compiler does not change the order.
-<pre>
 typedef unsigned long long Tsc_t;
@@ Line 39: / Line 40: @@
    return ( (unsigned long long)lo)|( ((unsigned long long)hi)<<32 );
+}
-</pre>
+</syntaxhighlight>
-<pre>
+<syntaxhighlight lang="c">
 #include <stdio.h>
@@ Line 65: / Line 68: @@
    return 0;
+}
-</pre>
+</syntaxhighlight>
-<pre>
 #include <stdio.h>
 #include <unistd.h>
@@ Line 79: / Line 84: @@
    return ( (unsigned long long)lo)|( ((unsigned long long)hi)<<32 );
+}
 int main(void) {
@@ Line 93: / Line 97: @@
    return 0;
+}
-</pre>
+</syntaxhighlight>

@@ Line 31: / Line 31: @@
 <pre>
-Tsc_t readTsc(void)
+typedef unsigned long long Tsc_t;
+{
    unsigned hi, lo;
    __asm__ __volatile__ ("rdtsc" : "=a"(lo), "=d"(hi));
    return ( (unsigned long long)lo)|( ((unsigned long long)hi)<<32 );
+}
 </pre>

@@ Line 13: / Line 13: @@
 using the RDTSCP instruction, which is a serializing variant of the RDTSC instruction. ->  force every preceding instruction to complete
- the time-stamp counter increments at a constant rate. That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may differ from the maximum qualified frequency of the processor.
+the time-stamp counter increments at a constant rate. That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may differ from the maximum qualified frequency of the processor.
 Since the family 10h (Barcelona/Phenom), AMD chips feature a constant TSC.

← Older revision		Revision as of 09:20, 6 November 2014
Line 1:		Line 1:
	The Time Stamp Counter (TSC) is a 64-bit register present in most modern x86 processors.		The Time Stamp Counter (TSC) is a 64-bit register present in most modern x86 processors.
		+
		+	It counts the number of cycles since reset.
		+
		+	The instruction RDTSC returns the TSC in EDX:EAX
		+
		+	supported out-of-order execution
		+
		+	not necessarily performed in the order they appear in the executable
		+
		+	This can cause RDTSC to be executed later or earlier -> misleading cycle count.
		+
		+	using the RDTSCP instruction, which is a serializing variant of the RDTSC instruction. -> force every preceding instruction to complete
		+
		+	the time-stamp counter increments at a constant rate. That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may differ from the maximum qualified frequency of the processor.
		+
		+	Since the family 10h (Barcelona/Phenom), AMD chips feature a constant TSC.
		+
		+	----
		+
		+	From Nehalem
		+
		+	By default the TSC is synchronized across all cores. However, the TSC value of a core could be changed by some software subsystem using the WRMSR instruction. Take a look at quotes below and I hope they finally answer your question:
		+
		+	Intel(R) 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B & 3C):
		+	System Programming Guide
		+
		+	----
		+
		+	Need to use "volatile" variables so that the compiler does not change the order.
		+
		+	<pre>
		+	Tsc_t readTsc(void)
		+	{
		+	unsigned hi, lo;
		+	__asm__ __volatile__ ("rdtsc" : "=a"(lo), "=d"(hi));
		+	return ( (unsigned long long)lo)\|( ((unsigned long long)hi)<<32 );
		+	}
		+	<\pre>