<?xml version="1.0"?>
<feed xmlns="http://www.w3.org/2005/Atom" xml:lang="en">
	<id>http://tuxamito.com/wiki/index.php?action=history&amp;feed=atom&amp;title=Selfmade_Computer</id>
	<title>Selfmade Computer - Revision history</title>
	<link rel="self" type="application/atom+xml" href="http://tuxamito.com/wiki/index.php?action=history&amp;feed=atom&amp;title=Selfmade_Computer"/>
	<link rel="alternate" type="text/html" href="http://tuxamito.com/wiki/index.php?title=Selfmade_Computer&amp;action=history"/>
	<updated>2026-05-06T04:16:22Z</updated>
	<subtitle>Revision history for this page on the wiki</subtitle>
	<generator>MediaWiki 1.31.12</generator>
	<entry>
		<id>http://tuxamito.com/wiki/index.php?title=Selfmade_Computer&amp;diff=47&amp;oldid=prev</id>
		<title>Daniel: Created page with &quot;I have always been interested in CPU architecture. In order to understand better how a CPU internally works I decided to design and build my own computer just using discrete l...&quot;</title>
		<link rel="alternate" type="text/html" href="http://tuxamito.com/wiki/index.php?title=Selfmade_Computer&amp;diff=47&amp;oldid=prev"/>
		<updated>2013-05-22T08:41:04Z</updated>

		<summary type="html">&lt;p&gt;Created page with &amp;quot;I have always been interested in CPU architecture. In order to understand better how a CPU internally works I decided to design and build my own computer just using discrete l...&amp;quot;&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;I have always been interested in CPU architecture. In order to understand better how a CPU internally works I decided to design and build my own computer just using discrete logic. For many people this might sound as a lost of time... but some people entertain themselves with sudokus! :)&lt;br /&gt;
&lt;br /&gt;
==TH-C01==&lt;br /&gt;
Full details of [[TH-C01]]&lt;br /&gt;
&lt;br /&gt;
====Definition====&lt;br /&gt;
* 8 bit ALU&lt;br /&gt;
* 8 bit Data bus&lt;br /&gt;
* 16 bit Address bus (MAX 64k bytes RAM)&lt;br /&gt;
* 8 x 8 bit registers (R0..R7) + (R6+R7 as address pointer)&lt;br /&gt;
* Dedicated Stack Pointer&lt;br /&gt;
* Dedicated PC&lt;br /&gt;
* Interruption control&lt;br /&gt;
* Expected 100 Khz&lt;br /&gt;
* RISC-like architecture with 3 to 5 cycles per operation&lt;br /&gt;
&lt;br /&gt;
====STATUS====&lt;br /&gt;
* Definition: Finished&lt;br /&gt;
* Design: Final Design&lt;br /&gt;
* Implementation: Early Implementation&lt;br /&gt;
* Tools:&lt;br /&gt;
** Assembler: Started&lt;br /&gt;
&lt;br /&gt;
==TH-C02==&lt;br /&gt;
====Definition====&lt;br /&gt;
* 24 bit ALU&lt;br /&gt;
* 24 bit Data bus&lt;br /&gt;
* 24 bit Address bus&lt;br /&gt;
* RISC architecture&lt;br /&gt;
* Pipelining&lt;br /&gt;
&lt;br /&gt;
====STATUS====&lt;br /&gt;
* Design: &lt;br /&gt;
* Implementation: &lt;br /&gt;
* Tools:&lt;br /&gt;
** Assembler&lt;br /&gt;
** Compiler&lt;/div&gt;</summary>
		<author><name>Daniel</name></author>
		
	</entry>
</feed>