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Daniel: Blanked the page

2013-05-22T08:41:13Z

Blanked the page

Daniel: /* TH-C01 */

2013-05-08T14:28:43Z

‎TH-C01

Daniel: Created page with "I have always been interested in CPU architecture. In order to understand better how a CPU internally works I decided to design and build my own computer just using discrete l..."

2013-05-08T14:24:30Z

Created page with "I have always been interested in CPU architecture. In order to understand better how a CPU internally works I decided to design and build my own computer just using discrete l..."

New page

I have always been interested in CPU architecture. In order to understand better how a CPU internally works I decided to design and build my own computer just using discrete logic. For many people this might sound as a lost of time... but some people entertain themselves with sudokus! :)

==TH-C01==
====Definition====
* 8 bit ALU
* 8 bit Data bus
* 16 bit Address bus (MAX 64k bytes RAM)
* 8 x 8 bit registers (R0..R7) + (R6+R7 as address pointer)
* Dedicated Stack Pointer
* Dedicated PC
* Interruption control
* Expected 100 Khz
* RISC-like architecture with 3 to 5 cycles per operation

====STATUS====
* Definition: Finished
* Design: Final Design
* Implementation: Early Implementation
* Tools:
** Assembler: Started

==TH-C02==
====Definition====
* 24 bit ALU
* 24 bit Data bus
* 24 bit Address bus
* RISC architecture
* Pipelining

====STATUS====
* Design:
* Implementation:
* Tools:
** Assembler
** Compiler

← Older revision		Revision as of 08:41, 22 May 2013
Line 1:		Line 1:
−	I have always been interested in CPU architecture. In order to understand better how a CPU internally works I decided to design and build my own computer just using discrete logic. For many people this might sound as a lost of time... but some people entertain themselves with sudokus! :)

−	~~==TH-C01==~~
−	~~Full details of [[TH-C01]]~~
−
−	~~====Definition====~~
−	* 8 bit ALU
−	* 8 bit Data bus
−	* 16 bit Address bus (MAX 64k bytes RAM)
−	* 8 x 8 bit registers (R0..R7) + (R6+R7 as address pointer)
−	* Dedicated Stack Pointer
−	* Dedicated PC
−	* Interruption control
−	* Expected 100 Khz
−	* RISC-like architecture with 3 to 5 cycles per operation
−
−	~~====STATUS====~~
−	* Definition: Finished
−	* Design: Final Design
−	* Implementation: Early Implementation
−	* Tools:
−	** Assembler: Started
−
−	~~==TH-C02==~~
−	~~====Definition====~~
−	* 24 bit ALU
−	* 24 bit Data bus
−	* 24 bit Address bus
−	* RISC architecture
−	* Pipelining
−
−	~~====STATUS====~~
−	* Design:
−	* Implementation:
−	* Tools:
−	** Assembler
−	** Compiler

@@ Line 2: / Line 2: @@
 ==TH-C01==
 ====Definition====
 * 8 bit ALU